The availability of high-speed serial inputs/outputs and general purpose programmable logic makes FPGAs (field programmable gate arrays) ideal devices to be used for acquisition, mixing, storage, editing, processing and format conversion applications. Simpler applications use FPGAs to acquire SDI data from one or more SD (standard definition), HD (high definition) or 3G (3-Gigabit HD) sources, perform simple processing and re-transmit the video data in SDI format. Such applications require an SDI PHY (physical layer) interface and some basic processing blocks like a color space converter. In more complex applications, the acquired video is taken through multiple processing phases, like de-interlacing, video format conversion, filtering, scaling, graphics mixing and picture-in-picture display. FPGA devices can also be used as a bridge between SDI video sources and backplane protocols such as PCI Express or Ethernet, with or without any additional video processing.
- Interface: SMPTE 259M-2006 [1] (SD), SMPTE 292M-1998 [2] (HD) and SMPTE 424 M [3] (3G)
- SD source formats: SMPTE 125M [4] and SMPTE 267M [5] (13.5 Mhz only)
- HD source formats: SMPTE 260M [6], SMPTE 274M [7], SMPTE 295M [8] and SMPTE 296M [9]
- 3G source formats: SMPTE 425M [10]
The IP, when connected with the LatticeECP3 SERDES, can transmit and/or receive any of the supported video standards and formats through a common physical serial interface. The IP core can automatically scan and lock on to any of the supported video streams. Receiving multiple standards requires appropriate external clocks to be supplied by the application in response to commands from the IP core.
Features
- Dynamic reception of multiple interface standards over the same physical cable: SD-SDI, HD-SDI and 3G-SDI interfaces
- Automatic Rx (receive) rate detection and dynamic Tx (transmit) rate selection
- Multiple SD source formats support: SMPTE 125M [4] and SMPTE 267M [5] (13.5 MHz only)
- Multiple HD source formats support: SMPTE 260M [6], SMPTE 274M [7], SMPTE 295M [8] and SMPTE 296M [9]
- Support for 3G source formats, including 3G Level-B format: SMPTE 425M [10]
- Word alignment and timing reference sequence (TRS) detection
- Field, vertical blanking (vblank) and horizontal blanking (hblank) timing signals generation
- CRC computation, error checking and insertion for HD/3GLine number (LN) decoding and encoding for HD/3G
- Custom source format support for HD/3G
- Video Payload Identifier (VPID) insertion and extraction for HD/3G
- 10-bit parallel input/output support for SD
- Soft-logic based low data-rate (LDR) serializer for SD transmission
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